Renesas R5S72624 User Manual
Section 26 USB 2.0 Host/Function Module
Page 1382 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
26.3.11
Interrupt Enable Register 1 (INTENB1)
INTENB1 is a register that enables or disables the various interrupts when the host controller
function is selected. On detecting the interrupt corresponding to the bit in this register that has
been set to 1, this module generates the USB interrupt.
function is selected. On detecting the interrupt corresponding to the bit in this register that has
been set to 1, this module generates the USB interrupt.
This module sets 1 to each status bit in INTSTS1 when a detection condition of the corresponding
interrupt source has been satisfied regardless of the set value in INTENB1 (regardless of whether
the interrupt output is enabled or disabled).
interrupt source has been satisfied regardless of the set value in INTENB1 (regardless of whether
the interrupt output is enabled or disabled).
While the status bit in INTSTS1 corresponding to the interrupt source indicates 1, this module
generates the USB interrupt when the corresponding interrupt enable bit in INTENB1 is modified
from 0 to 1.
generates the USB interrupt when the corresponding interrupt enable bit in INTENB1 is modified
from 0 to 1.
When the function controller function is selected, the interrupts should not be enabled. This
register is initialized by a power-on reset.
register is initialized by a power-on reset.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit:
Initial value:
R/W:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R/W
R
R/W
R/W
R
R
R
R
R/W
R/W
R/W
R
R
R
R
—
BCHGE
—
DTCHE
ATT
CHE
—
—
—
EOF
ERRE
SIGNE SACKE
—
—
—
—
—
Bit Bit
Name
Initial
Value
Value
R/W Description
15
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
always be 0.
14
BCHGE
0
R/W
USB Bus Change Interrupt Enable
Enables or disables the USB interrupt request when
the BCHG interrupt is detected.
the BCHG interrupt is detected.
0: Interrupt request disabled
1: Interrupt request enabled
13
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
always be 0.
12
DTCHE
0
R/W
Disconnection Detection Interrupt Enable
Enables or disables the USB interrupt request when
the DTCH interrupt is detected.
the DTCH interrupt is detected.
0: Interrupt request disabled
1: Interrupt request enabled