Renesas R5S72624 User Manual
Section 26 USB 2.0 Host/Function Module
R01UH0134EJ0400 Rev. 4.00
Page 1441 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
26.3.35
Pipe Timing Control Register (PIPEPERI)
PIPEPERI is a register that selects whether the buffer is flushed or not when an interval error
occurred during isochronous IN transfer, and sets the interval error detection interval for PIPE1 to
PIPE9.
occurred during isochronous IN transfer, and sets the interval error detection interval for PIPE1 to
PIPE9.
This register is initialized by a power-on reset.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit:
Initial value:
R/W:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R/W
R
R
R
R
R
R
R
R
R
R/W
R/W
R/W
—
—
—
IFIS
—
—
—
—
—
—
—
—
—
IITV[2:0]
Bit Bit
Name
Initial
Value
Value
R/W Description
15 to 13
All
0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
These bits are always read as 0. The write value should
always be 0.
12
IFIS
0
R/W
Isochronous IN Buffer Flush
Specifies whether to flush the buffer when the pipe
selected by the PIPESEL bits (selected pipe) is used for
isochronous IN transfers.
0: The buffer is not flushed.
Specifies whether to flush the buffer when the pipe
selected by the PIPESEL bits (selected pipe) is used for
isochronous IN transfers.
0: The buffer is not flushed.
1: The buffer is flushed.
When the function controller function is selected and the
selected pipe is for isochronous IN transfers, this module
automatically clears the FIFO buffer when this module
fails to receive the IN token from the USB host within the
interval set by the IITV bits in terms of (
When the function controller function is selected and the
selected pipe is for isochronous IN transfers, this module
automatically clears the FIFO buffer when this module
fails to receive the IN token from the USB host within the
interval set by the IITV bits in terms of (
) frames.
In double buffer mode (DBLB = 1), this module only
clears the data in the plane used earlier.
This module clears the FIFO buffer on receiving the SOF
packet immediately after the (
clears the data in the plane used earlier.
This module clears the FIFO buffer on receiving the SOF
packet immediately after the (
) frame in which this
module has expected to receive the IN token. Even if the
SOF packet is corrupted, this module also clears the
FIFO buffer at the right timing to receive the SOF packet
by using the internal interpolation.
When the host controller function is selected, set this bit
to 0.
When the selected pipe is not for the isochronous
transfer, set this bit to 0.
SOF packet is corrupted, this module also clears the
FIFO buffer at the right timing to receive the SOF packet
by using the internal interpolation.
When the host controller function is selected, set this bit
to 0.
When the selected pipe is not for the isochronous
transfer, set this bit to 0.