Renesas R5S72624 User Manual
Section 33 Power-Down Modes
R01UH0134EJ0400 Rev. 4.00
Page 1775 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
4
MSTP7
0
R/W
Module Stop 7
When the MSTP7 bit is set to 1, the clock supply to the
FPU is halted. After setting the MSTP7 bit to 1, the
MSTP7 bit cannot be cleared by writing 0. This means
that, after the clock supply to the FPU is halted by
setting the MSTP7 bit to 1, the supply cannot be
restarted by clearing the MSTP7 bit to 0.
FPU is halted. After setting the MSTP7 bit to 1, the
MSTP7 bit cannot be cleared by writing 0. This means
that, after the clock supply to the FPU is halted by
setting the MSTP7 bit to 1, the supply cannot be
restarted by clearing the MSTP7 bit to 0.
To restart the clock supply to the FPU after it was
halted, reset the LSI by a power-on reset.
halted, reset the LSI by a power-on reset.
0: The FPU runs.
1: Clock supply to the FPU is halted.
3 to 0
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
always be 0.
33.2.3
Standby Control Register 3 (STBCR3)
STBCR3 is an 8-bit readable/writable register that controls the operation of modules.
Note: When writing to this register, see section 33.4, Usage Notes.
7
6
5
4
3
2
1
0
Bit:
Initial value:
R/W:
0
1
1
1
1
1
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
MSTP
35
MSTP
33
MSTP
32
-
HIZ
MSTP
30
MSTP
34
MSTP
36