Renesas R5S72624 User Manual
Section 7 Interrupt Controller
Page 168 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
7.3.5
IRQ Interrupt Request Register (IRQRR)
IRQRR is a 16-bit register that indicates interrupt requests from external input pins IRQ7 to IRQ0.
If edge detection is set for the IRQ7 to IRQ0 interrupts, writing 0 to the IRQ7F to IRQ0F bits after
reading IRQ7F to IRQ0F = 1 cancels the retained interrupts.
If edge detection is set for the IRQ7 to IRQ0 interrupts, writing 0 to the IRQ7F to IRQ0F bits after
reading IRQ7F to IRQ0F = 1 cancels the retained interrupts.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Note:
Only 0 can be written to clear the flag after 1 is read.
*
Bit:
Initial value:
R/W:
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
-
-
-
-
-
-
-
-
IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
15 to 8
All
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
should always be 0.
7 IRQ7F
0 R/(W)* IRQ Interrupt Request
These bits indicate the status of the IRQ7 to IRQ0
interrupt requests.
interrupt requests.
Level detection:
0: IRQn interrupt request has not occurred
[Clearing condition]
IRQn input is high
1: IRQn interrupt has occurred
IRQn input is high
1: IRQn interrupt has occurred
[Setting condition]
IRQn input is low
Edge detection:
IRQn input is low
Edge detection:
0: IRQn interrupt request is not detected
[Clearing conditions]
Cleared by reading IRQnF while IRQnF = 1, then
Cleared by reading IRQnF while IRQnF = 1, then
writing 0 to IRQnF
Cleared by executing IRQn interrupt exception
handling
1: IRQn interrupt request is detected
[Setting condition]
Edge corresponding to IRQn1S or IRQn0S of
Edge corresponding to IRQn1S or IRQn0S of
ICR1 has occurred at IRQn pin
6 IRQ6F
0 R/(W)*
5 IRQ5F
0 R/(W)*
4 IRQ4F
0 R/(W)*
3 IRQ3F
0 R/(W)*
2 IRQ2F
0 R/(W)*
1 IRQ1F
0 R/(W)*
0 IRQ0F
0 R/(W)*
[Legend]
n = 7 to 0
n = 7 to 0