Renesas R5S72624 User Manual

 

Section 11   Multi-Function Timer Pulse Unit 2 

 

R01UH0134EJ0400  Rev. 4.00  

 

Page 469 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. 
This module has six TSR registers, two for channel 0 and one each for channels 1 to 4. 

  TSR_0, TSR_1, TSR_2, TSR_3, TSR_4 

Bit:

Initial value:

R/W:

7

6

5

4

3

2

1

0

R

R

R/(W)*

1

R/(W)*

1

R/(W)*

1

R/(W)*

1

R/(W)*

1

R/(W)*

1

1

1

0

0

0

0

0

0

Note:

Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.

1.

TCFD

-

TCFU

TCFV

TGFD

TGFC

TGFB

TGFA

 

 

7 

TCFD 

1 

R 

Count Direction Flag 

Status flag that shows the direction in which TCNT 
counts in channels 1 to 4. 

In channel 0, bit 7 is reserved. It is always read as 1 
and the write value should always be 1. 

0: TCNT counts down 

1: TCNT counts up 

6 



 1 

R 

Reserved 

This bit is always read as 1. The write value should 
always be 1. 

5 TCFU  0  R/(W)*

1

Underflow Flag 

Status flag that indicates that TCNT underflow has 
occurred when channels 1 and 2 are set to phase 
counting mode. Only 0 can be written, for flag clearing.

In channels 0, 3, and 4, bit 5 is reserved. It is always 
read as 0 and the write value should always be 0. 

[Clearing condition] 

  When 0 is written to TCFU after reading TCFU = 1*

2

[Setting condition] 

  When the TCNT value underflows (changes from 

H'0000 to H'FFFF)