Renesas R5S72624 User Manual

 

 

Section 11   Multi-Function Timer Pulse Unit 2 
 

Page 614 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

In complementary PWM mode, when output waveform control during synchronous counter 
clearing is enabled (WRE in the TWCR register set to 1), the following problems may occur when 
condition (1) or condition (2), below, is satisfied. 

  Dead time for the PWM output pins may be too short (or nonexistent). 
  Active-level output from the PWM negative-phase pins may occur outside the correct active-

level output interval 

 
Condition (1):  When synchronous clearing occurs in the PWM output dead time interval within 

initial output suppression interval (10) (figure 11.113). 

Condition (2): When synchronous clearing occurs within initial output suppression interval (10) or 

(11) and TGRB_3 

 TDDR, TGRA_4  TDDR, or TGRB_4  TDDR is true 

(figure 11.114) 

TCNT3

TCNT4

TDDR

TGRA_3

TGR

TDDR

0

Synchronous clearing

 Dead 

time

Note:  PWM output is low-active.

PWM output 
(positive phase)

PWM output 
(negative phase)

Shortened dead time

Initial output suppression

Tb interval

Tb interval

(10)

(10)

(11)

(11)