Renesas R5S72624 User Manual

 

Section 16   Renesas Serial Peripheral Interface 

 

R01UH0134EJ0400  Rev. 4.00  

 

Page 789 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

SPDR is a buffer that holds data for transmission and reception. 

The transmit buffer (SPTX) and receive buffer (SPRX) are independent and are mapped to SPDR. 

SPDR should be read or written to in byte, word, or longword units according to the access width 
specification bit (SPLW) in the data control register (SPDCR). 

The bit length to be used is determined by the data length specification bits (SPB3 to SPB0) in the 
command register (SPCMD). 

When data is written to SPDR, the data will be written to the transmit buffer from SPDR if the 
transmit buffer has a space equal to or more than the SPDR access width. If there is not enough 
space, data will not be written to the transmit buffer. Even if an attempt is made to write data to 
the buffer, the data is ignored. 

When data is read from SPDR, receive data in the receive buffer will be read. If SPDR is read 
when there is no receive data in the receive buffer, the read value is undefined. 

When SPDR is written to with the longword-, word-, or byte-access width, the transmit data 
should be written to the following bits. If data is written to the other bits, the data is not 
guaranteed. 

  Longword: Bits 31 to 0 
  Word: Bits 31 to 16 
  Byte: Bits 31 to 24 
 
When SPDR is read with the longword-, word-, or byte-access width, the receive data should be 
read from the following bits. If data is read from the other bits, the data is not guaranteed. 

  Longword: Bits 31 to 0 
  Word: Bits 31 to 16 
  Byte: Bits 31 to 24