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Renesas R5S72644 User Manual

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Section 2   CPU 
 
Page 72 of 2108 
 
R01UH0134EJ0400  Rev. 4.00 
 
 Sep 
24, 
2014 
SH7262 Group, SH7264 Group
 
Classification 
 
Types 
Operation 
Code 
 
Function 
No. of 
Instructions
System  
control 
14 
CLRT 
T bit clear 
36 
 
CLRMAC 
MAC register clear 
 
LDBANK 
Register restoration from specified register 
bank entry 
 
 
LDC 
Load to control register 
 
 
 
LDS 
Load to system register 
 
  
NOP 
No 
operation 
 
 
 
RESBANK  Register restoration from register bank 
 
 
 
RTE 
Return from exception handling 
 
 
 
SETT 
T bit set 
 
 
 
SLEEP 
Transition to power-down mode 
 
 
 
STBANK 
Register save to specified register bank entry 
 
 
 
STC 
Store control register data 
 
 
 
STS 
Store system register data 
 
 
 
TRAPA 
Trap exception handling 
 
Floating-point 
instructions 
19 FABS  Floating-point absolute value 
48 
 FADD 
Floating-point 
addition 
 
  
FCMP 
Floating-point 
comparison 
 
 
 
FCNVDS 
Conversion from double-precision to single-
precision 
 
 
 
FCNVSD 
Conversion from single-precision to double -
precision 
 
  
FDIV 
Floating-point 
division 
 
 
 
FLDI0 
Floating-point load immediate 0 
 
 
 
FLDI1 
Floating-point load immediate 1 
 
 
 
FLDS 
Floating-point load into system register FPUL 
 
 
 
FLOAT 
Conversion from integer to floating-point 
 
 
 
FMAC 
Floating-point multiply and accumulate 
operation 
 
 
 
FMOV 
Floating-point data transfer 
 
  
FMUL 
Floating-point 
multiplication 
 
 
 
FNEG 
Floating-point sign inversion