Renesas R5S72644 User Manual
Page 2098 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
Calculating exception handling vector
table addresses ........................................ 136
CAN bus interface ................................ 1079
CAN interface ......................................... 985
Canceling software standby mode
(watchdog timer) .................................... 670
Cascaded operation ................................. 519
Caution on period setting ........................ 599
CD-ROM decoder ................................ 1191
Changing the division ratio ..................... 125
Changing the frequency .......................... 125
Clock frequency control circuit .............. 117
Clock operating modes ........................... 119
Clock pulse generator ............................. 115
Clock timing ......................................... 1974
Clocked synchronous serial format ........ 877
CMCNT count timing ............................. 655
Coherency of cache and external
memory or large-capacity on-chip
RAM ....................................................... 223
Command access mode ........................ 1324
Communications protocol ..................... 1088
Compare match timer ............................. 649
Complementary PWM mode .................. 539
Conditions for determining number of
idle cycles ............................................... 357
Configuration mode ................................ 929
Configuration of controller area
network ................................................. 1054
Conflict between byte-write and
count-up processes of CMCNT .............. 660
Conflict between word-write and
count-up processes of CMCNT .............. 659
Conflict between write and
compare-match processes of CMCNT .... 658
Control signal timing ............................ 1979
Controller area network .......................... 981
Controller area network control
registers ................................................ 1004
table addresses ........................................ 136
CAN bus interface ................................ 1079
CAN interface ......................................... 985
Canceling software standby mode
(watchdog timer) .................................... 670
Cascaded operation ................................. 519
Caution on period setting ........................ 599
CD-ROM decoder ................................ 1191
Changing the division ratio ..................... 125
Changing the frequency .......................... 125
Clock frequency control circuit .............. 117
Clock operating modes ........................... 119
Clock pulse generator ............................. 115
Clock timing ......................................... 1974
Clocked synchronous serial format ........ 877
CMCNT count timing ............................. 655
Coherency of cache and external
memory or large-capacity on-chip
RAM ....................................................... 223
Command access mode ........................ 1324
Communications protocol ..................... 1088
Compare match timer ............................. 649
Complementary PWM mode .................. 539
Conditions for determining number of
idle cycles ............................................... 357
Configuration mode ................................ 929
Configuration of controller area
network ................................................. 1054
Conflict between byte-write and
count-up processes of CMCNT .............. 660
Conflict between word-write and
count-up processes of CMCNT .............. 659
Conflict between write and
compare-match processes of CMCNT .... 658
Control signal timing ............................ 1979
Controller area network .......................... 981
Controller area network control
registers ................................................ 1004
Controller area network mailbox
registers ................................................. 1025
Controller area network memory map .... 987
Controller area network timer
registers ................................................. 1039
CPU .......................................................... 49
Crystal oscillator ..................................... 117
CSn assert period expansion ................... 300
Cycle steal mode ..................................... 421
registers ................................................. 1025
Controller area network memory map .... 987
Controller area network timer
registers ................................................. 1039
CPU .......................................................... 49
Crystal oscillator ..................................... 117
CSn assert period expansion ................... 300
Cycle steal mode ..................................... 421
D
Data array ........................................ 210, 225
Data array read ........................................ 225
Data array write ...................................... 226
Data format ............................................. 815
Data format in registers ............................. 54
Data formats in memory ........................... 54
Data transfer instructions .......................... 75
Data transfer with interrupt request
signals ..................................................... 206
DC characteristics ................................. 1963
Decompression unit .............................. 1669
Deep power-down mode ......................... 341
Deep standby mode ............................... 1811
Definitions of A/D conversion
accuracy ................................................ 1281
Delayed branch instructions ...................... 57
Denormalized numbers ........................... 100
Direct memory access controller............. 371
Direct memory access controller
interface ................................................ 1078
Direct memory access controller
timing .................................................... 2015
Displacement accessing ............................ 59
Divider 1 ................................................. 117
Divider 2 ................................................. 117
DMA transfer flowchart .......................... 409
DREQ pin sampling timing .................... 426
Dual address mode .................................. 418
Data array read ........................................ 225
Data array write ...................................... 226
Data format ............................................. 815
Data format in registers ............................. 54
Data formats in memory ........................... 54
Data transfer instructions .......................... 75
Data transfer with interrupt request
signals ..................................................... 206
DC characteristics ................................. 1963
Decompression unit .............................. 1669
Deep power-down mode ......................... 341
Deep standby mode ............................... 1811
Definitions of A/D conversion
accuracy ................................................ 1281
Delayed branch instructions ...................... 57
Denormalized numbers ........................... 100
Direct memory access controller............. 371
Direct memory access controller
interface ................................................ 1078
Direct memory access controller
timing .................................................... 2015
Displacement accessing ............................ 59
Divider 1 ................................................. 117
Divider 2 ................................................. 117
DMA transfer flowchart .......................... 409
DREQ pin sampling timing .................... 426
Dual address mode .................................. 418