Renesas R5S72644 User Manual
Section 9 Bus State Controller
Page 230 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
6. PCMCIA direct interface
Supports the IC memory card and I/O card interface defined in JEIDA specifications Ver.
4.2 (PCMCIA2.1 Rev. 2.1).
4.2 (PCMCIA2.1 Rev. 2.1).
Wait-cycle insertion controllable by program.
7. SRAM interface with byte selection
Can connect directly to a SRAM with byte selection.
8. Burst ROM interface (clocked synchronous)
Can connect directly to a burst ROM of the clocked synchronous type.
9. Bus arbitration
Shares all of the resources with other CPU and outputs the bus enable after receiving the
bus request from external devices.
bus request from external devices.
10. Refresh function
Supports the auto-refresh and self-refresh functions.
Specifies the refresh interval using the refresh counter and clock selection.
Can execute concentrated refresh by specifying the refresh counts (1, 2, 4, 6, or 8).
11. Usage as interval timer for refresh counter
Generates an interrupt request at compare match.