Renesas R5S72644 User Manual
Section 16 Renesas Serial Peripheral Interface
R01UH0134EJ0400 Rev. 4.00
Page 837 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
(f) SSL Negation Delay (t2)
The SSL negation delay value in master mode depends on SLNDEN bit settings in the command
register (SPCMD) and on SSL negation delay register (SSLND) settings. This module determines
the SPCMD to be referenced during serial transfer by pointer control, and determines an SSL
negation delay value during serial transfer by using the SLNDEN bit in the selected SPCMD and
SSLND, as shown in table 16.9. For a definition of SSL negation delay, see section 16.4.4,
Transfer Format.
register (SPCMD) and on SSL negation delay register (SSLND) settings. This module determines
the SPCMD to be referenced during serial transfer by pointer control, and determines an SSL
negation delay value during serial transfer by using the SLNDEN bit in the selected SPCMD and
SSLND, as shown in table 16.9. For a definition of SSL negation delay, see section 16.4.4,
Transfer Format.
Table 16.9 Relationship among SLNDEN and SSLND Settings and SSL Negation Delay
Values
SLNDEN
SSLND
SSL Negation Delay Value
0
000 to 111
1 RSPCK
1 000
1
RSPCK
001 2
RSPCK
010 3
RSPCK
011 4
RSPCK
100 5
RSPCK
101 6
RSPCK
110 7
RSPCK
111
8
RSPCK