Renesas R5S72621 User Manual

 

Section 19   Serial I/O with FIFO 

 

R01UH0134EJ0400  Rev. 4.00  

 

Page 975 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

This module has one type of interrupt. 

Interrupts can be issued by several requests. Each source is shown as an status in SISTR. Table 
19.11 lists the interrupt requests. 

Table 19.11  Interrupt Requests 

1 Transmission  TDREQ  Transmit 

FIFO 

transfer 

request 

The transmit FIFO stores data of 
specified size or more. 

2 

TFEMP 

Transmit FIFO empty 

The transmit FIFO is empty. 

3 

Reception 

RDREQ 

Receive FIFO transfer 
request 

The receive FIFO stores data of 
specified size or more. 

4 

RFFUL 

Receive FIFO full 

The receive FIFO is full. 

5 Error 

TFUDF  Transmit 

FIFO 

underflow 

Serial data transmit timing has arrived 
while the transmit FIFO is empty. 

6 

TFOVF 

Transmit FIFO overflow Write to the transmit FIFO is 

performed while the transmit FIFO is 
full. 

7 

RFOVF 

Receive FIFO overflow Serial data is received while the 

receive FIFO is full. 

8 RFUDF 

Receive 

FIFO 

underflow 

The receive FIFO is read while the 
receive FIFO is empty. 

9 

 

FSERR 

FS error 

A synchronous signal is input before 
the specified bit number has been 
passed (in slave mode). 

 

Whether the interrupt is issued or not by the request is determined by the SIIER settings. If an 
interrupt request is generated when the corresponding bit in SIIER is set to 1, this module issues 
the interrupt.