Renesas R5S72621 User Manual
Section 20 Controller Area Network
Page 1058 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Registers
Status Mode
MCR
GSR
GSR
IRR
IMR BCR
IMR BCR
MBIMR
timer
TT_register
Flag_
register
register
Mailbox
(ctrl0, LAFM)
(ctrl0, LAFM)
Mailbox
(data)
(data)
Mailbox
(ctrl1)
(ctrl1)
Mailbox
Trigger
Time TT
control
Trigger
Time TT
control
Reset
yes yes yes yes
yes yes
yes yes
yes
Transmission
Reception
Halt Request
Reception
Halt Request
yes yes no*
1
yes
yes
no*
1
yes*
2
yes*
2
no*
1
yes*
2
yes*
2
Halt yes
yes
no*
1
yes
yes
yes
yes
yes
yes
Sleep yes
yes
no
no no
no
no
no no
Notes: 1. No hardware protection.
2.
When TXPR is not set.
20.4.3
Message Transmission Sequence
Message Transmission Request
The following sequence is an example to transmit a CAN frame onto the bus. As described in the
previous register section, please note that IRR8 is set when one of the TXACK or ABACK bits is
set, meaning one of the Mailboxes has completed its transmission or transmission abortion and is
now ready to be updated for the next transmission, whereas, the GSR2 means that there is
currently no transmission request made (No TXPR flags set).
The following sequence is an example to transmit a CAN frame onto the bus. As described in the
previous register section, please note that IRR8 is set when one of the TXACK or ABACK bits is
set, meaning one of the Mailboxes has completed its transmission or transmission abortion and is
now ready to be updated for the next transmission, whereas, the GSR2 means that there is
currently no transmission request made (No TXPR flags set).