Renesas R5S72621 User Manual
Section 20 Controller Area Network
R01UH0134EJ0400 Rev. 4.00
Page 1073 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
20.4.4
Message Receive Sequence
The diagram below shows the message receive sequence.
Controller Area Network
End Of Arbitration Field
Notes: 1. Only if CPU clears RXPR[N]/RFPR[N] at the same time that UMSR is set in overrun, RXPR[N]/RFPR[N] may be set again even though the
message has not been updated. TimeStamp may also be updated, however it can be read properly before clearing RXPR[N]/RFPR[N].
2. In case overwrite configuration (NMC = 1) is used for the Mailbox N the message must be discarded when UMSR[N] = 1, UMSR[N] cleared
and the full Interrupt Service Routine started again. In case of overrun configuration (NMC = 0) is used clear again RXPR[N]/RFPR[N]/
UMSR[N] when UMSR[N] = 1 and consider the message obsolate.
message has not been updated. TimeStamp may also be updated, however it can be read properly before clearing RXPR[N]/RFPR[N].
2. In case overwrite configuration (NMC = 1) is used for the Mailbox N the message must be discarded when UMSR[N] = 1, UMSR[N] cleared
and the full Interrupt Service Routine started again. In case of overrun configuration (NMC = 0) is used clear again RXPR[N]/RFPR[N]/
UMSR[N] when UMSR[N] = 1 and consider the message obsolate.
CAN Bus
End Of Frame
IDLE
Valid CAN-ID Received
Compare ID with
Mailbox[N] + LAFM[N]
(if MBC is config to receive)
Store Mailbox-Number[N]
and go back to idle state
•Store Message by Overwriting
•Set UMSR
•Set IRR9 (if MBIMR[N] = 0)
•Generate Interrupt Signal
(if IMR9 = 0)
•Set RXPR[N] (RFPR[N])
(if IMR9 = 0)
•Set RXPR[N] (RFPR[N])
•Set IRR1 (IRR2) (if MBIMR[N] = 0)
•Generate Interrupt Signal
(if IMR1 (IMR2) = 0)
(if IMR1 (IMR2) = 0)
•Reject Message
•Set UMSR
•Set IRR9 (if MBIMR[N] = 0)
•Generate Interrupt Signal
(if IMR9 = 0)
•Set RXPR[N] (RFPR[N]) *
(if IMR9 = 0)
•Set RXPR[N] (RFPR[N]) *
•Store Message
•Set RXPR[N] (RFPR[N])
•Set IRR1 (IRR2) (if MBIMR[N] = 0)
•Generate Interrupt Signal
(if IMR1 (IMR2) = 0)
(if IMR1 (IMR2) = 0)
Valid CAN Frame Received
Check and clear
UMSR[N]
**
Write 1 to RXPR[N]
Read Mailbox[N]
IRR[1]
set?
Read IRR
MSG
OverWrite or
OverRun?
(NMC)
OverWrite
OverRun
N = 0?
N = N - 1
No
No
No
No
Yes
Yes
Yes
Write 1 to RFPR[N]
Read Mailbox[N]
Read RFPR[N] = 1
Yes
Yes
CPU received interrupt due to CAN Message Reception
RXPR[N]
(RFPR[N])
Already Set?
ID Matched?
Interrupt signal
Interrupt signal
Interrupt signal
Loop (N = 31; N
≥
0; N = N - 1)
Read RXPR[N] = 1
Check and clear
UMSR[N]
**
Exit Interrupt Service
Routine
Figure 20.24 Message receive sequence