Renesas R5S72621 User Manual
Section 22 Renesas SPDIF Interface
R01UH0134EJ0400 Rev. 4.00
Page 1173 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
22.7.9
Receiver Channel 1 Audio Register (RLCA)
31
30
29
28
27
26
25
24
-
-
-
-
-
-
-
-
-
-
-
-
-
R
R
R
R
R
R
R
R
-
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
-
-
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
Audio PCM Data
Bit:
Initial value:
R/W:
Audio PCM Data
Bit:
Initial value:
R/W:
Audio PCM Data
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
31 to 24
R
Reserved
23 to 0 Audio PCM
Data
All 0
R
Audio PCM Data
LSB aligned PCM encoded audio data.