Renesas R5S72621 User Manual
Section 23 CD-ROM Decoder
R01UH0134EJ0400 Rev. 4.00
Page 1193 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
23.2
Block Diagrams
Figure 23.2 is a block diagram of the CD-ROM decoder functions of this LSI and the bus bridge
for connection to the bus, that is, of the elements required to implement the CD-ROM decoder
function.
for connection to the bus, that is, of the elements required to implement the CD-ROM decoder
function.
Bus bridge
Interrupt and direct memory access controller activation control
Interrupt controller, direct memory access controller
Register data
Stream data
Stream data
Stream data input control
Stream data output control
Descrambler
EDC
EDC
Sync code
detection/
maintenance
Mode
determination
Syndrome
calculator
Core of CD-ROM decoder
Memory
(2 buffers for ECC)
Memory
control
ECC control
Timing
generation
Internal bus
Figure 23.2 Block Diagram
The core of the CD-ROM decoder executes a series of processing required for CD-ROM
decoding, including descrambling, sync code detection, ECC correction (P- and Q-parity-based
correction), and EDC checking. The core includes sufficient memory to hold two sectors.
decoding, including descrambling, sync code detection, ECC correction (P- and Q-parity-based
correction), and EDC checking. The core includes sufficient memory to hold two sectors.