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Renesas R5S72621 User Manual

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Section 23   CD-ROM Decoder 
R01UH0134EJ0400  Rev. 4.00  
 
Page 1233 of 2108 
Sep 24, 2014 
 
 
 
SH7262 Group, SH7264 Group 
23.3.44
  Automatic Buffering Start Sector Setting: Frames Control Register (CBUFCTL3) 
The automatic buffering start sector setting: frames control register (CBUFCTL3) indicates the 
frames (1 frame = 1/75 second) value in the header for the first sector to be buffered 
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
BS_FRM[7:0]
 
 
Bit Bit 
Name 
Initial 
Value R/W 
Description 
7 to 0 
BS_FRM 
[7:0] 
All 0 
R/W 
Indicate setting of the frames (1/75 second) value in the 
header for the first sector to be buffered. 
 
23.3.45
  ISY Interrupt Source Mask Control Register (CROMST0M) 
The ISY interrupt source mask control register (CROMST0M) masks the ISY interrupt sources 
specified by the bits in CROMST0. 
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
-
-
ST_
SYILM
ST_
SYNOM
ST_
BLKSM
ST_
BLKLM
ST_
SECSM
ST_
SECLM
 
 
Bit Bit 
Name 
Initial 
Value 
R/W Description 
7, 6 
 All 
0 
R/W 
Reserved 
These bits are always read as 0.The write value should 
always be 0. 
5 
ST_SYILM  0 
R/W 
ISY interrupt ST_SYIL (bit 5 in the CROMST0 register) 
source mask 
4 ST_ 
SYNOM 
0 
R/W 
ISY interrupt ST_SYNO (bit 4 in the CROMST0 
register) source mask 
3 ST_ 
BLKSM 
0 
R/W 
ISY interrupt ST_BLKS (bit 3 in the CROMST0 register) 
source mask