Renesas R5S72621 User Manual

 
Section 2   CPU 
 

Page 92 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

The CPU has five processing states: reset, exception handling, bus-released, program execution, 
and power-down. Figure 2.6 shows the transitions between the states. 

Power-on reset from any state   

Manual reset from any state

Power-on reset state

Manual reset state

Program execution state

Sleep mode

Software standby mode

Exception

handling state

Exception

handling

source

occurs

Exception
handling
ends

NMI interrupt or 
IRQ interrupt occurs

Power-down state

Reset canceled

STBY bit cleared
for SLEEP
instruction

Reset state

Interrupt source or 
DMA address error occurs

NMI interrupt,  
realtime clock
alarm interrupt,
change on pins  
used for  
cancellation, 
and power-on 
reset

STBY bit set
and DEEP bit
cleared for SLEEP
instruction

STBY and DEEP bits set
for SLEEP
instruction

Deep standby mode

Bus-released state

Bus request
generated

Bus request
cleared

Bus request
generated

Bus request
cleared

Bus request
cleared

Bus request
generated