Renesas R5S72621 User Manual
Section 24 A/D Converter
Page 1280 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
24.5
Interrupt Sources and DMA Transfer Request
The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion.
An ADI interrupt request is generated if the ADIE bit is set to 1 when the ADF bit in ADCSR is
set to 1 on completion of A/D conversion. Note that the direct memory access controller can be
activated by an ADI interrupt depending on the setting of the direct memory access controller. In
this case, an interrupt is not issued to the CPU. If the setting to activate the direct memory access
controller has not been made, an interrupt request is sent to the CPU. Having the converted data
read by the direct memory access controller in response to an ADI interrupt enables continuous
conversion to be achieved without imposing a load on software.
An ADI interrupt request is generated if the ADIE bit is set to 1 when the ADF bit in ADCSR is
set to 1 on completion of A/D conversion. Note that the direct memory access controller can be
activated by an ADI interrupt depending on the setting of the direct memory access controller. In
this case, an interrupt is not issued to the CPU. If the setting to activate the direct memory access
controller has not been made, an interrupt request is sent to the CPU. Having the converted data
read by the direct memory access controller in response to an ADI interrupt enables continuous
conversion to be achieved without imposing a load on software.
In single mode, set the direct memory access controller so that DMA transfer initiated by an ADI
interrupt is performed only once. In the case of A/D conversion on multiple channels in scan mode
or multi mode, setting the DMA transfer count to one causes DMA transfer to finish after
transferring only one channel of data. To make the direct memory access controller transfer all
conversion data, set the ADDR where A/D conversion data is stored as the transfer source address,
and the number of converted channels as the transfer count.
interrupt is performed only once. In the case of A/D conversion on multiple channels in scan mode
or multi mode, setting the DMA transfer count to one causes DMA transfer to finish after
transferring only one channel of data. To make the direct memory access controller transfer all
conversion data, set the ADDR where A/D conversion data is stored as the transfer source address,
and the number of converted channels as the transfer count.
When the direct memory access controller is activated by ADI, the ADF bit in ADCSR is
automatically cleared to 0 when data is transferred by the direct memory access controller.
automatically cleared to 0 when data is transferred by the direct memory access controller.
Table 24.6 Relationship between Interrupt Sources and DMA Transfer Request
Name
Interrupt Source
Interrupt Flag
Direct Memory Access
Controller Activation
Controller Activation
ADI
A/D conversion end
ADF in ADCSR
Possible