Renesas R5S72621 User Manual
Section 25 NAND Flash Memory Controller
Page 1300 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
25.3.3
Command Code Register (FLCMCDR)
FLCMCDR is a 32-bit readable/writable register that specifies a command to be issued in
command access or sector access.
command access or sector access.
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CMD2[7:0]
CMD1[7:0]
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
31 to 16
All
0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
always be 0.
15 to 8
CMD2[7:0] H'00
R/W
Second Command Data
Specify a command code to be issued in the second
command stage.
command stage.
7 to 0
CMD1[7:0] H'00
R/W
First Command Data
Specify a command code to be issued in the first
command stage.
command stage.