Renesas R5S72621 User Manual

 

Section 25   NAND Flash Memory Controller 

R01UH0134EJ0400  Rev. 4.00  

 

Page 1341 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

Follow the procedure given below to write to the control-code area when the 4-symbol ECC 
circuit is in use. If this procedure is not followed, correct writing to the control-code area of the 
flash memory will not be possible. 

No

Yes

No

No

No

Yes

Yes

Yes

DMA

CPU

FLCMDCR

SCTCNT==

−−?

FLCMDCR

SCTCNT==0?

Start of writing to a sector or consecutive sectors

Start

End

Settings for DMA transfer

Source:High-speed RAM (RAM1)

Destination:FLECFIFO

Number of data for single-operand transfer:4 DMA

transfer mode:Pipeline transfer

Set the FLINTDMACR.FIFOTRG[0] bit (to 1).

To the flow for normal 

programming

Is the 4ECCEN 

bit in FLCMNCR 1?

If the 3-symbol ECC circuit has been enabled, 
the below flow for writting is not necessary.

Has the CPU or 

DMAC been selected 

in FLINTDMACR to 

handle transfer from 

FLECFIFO?

Normal settings for writing

Set FLTRCR to H'01.

Start the transfer.

Is the number of empty 
longwords indicated by 

FLDTCNTR.ECFLW eight?

Store the data to be written to the 

control code area in FLECFIFO.

Store the data to be written to 

the data area in FLDTFIFO.

Store the data to be written to the control-code 

area in high-speed internal RAM (RAM1).