Renesas R5S72621 User Manual
Section 26 USB 2.0 Host/Function Module
Page 1354 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Table 26.4 Register Bits Initialized by Writing USBE = 0 (when Host Controller Function
is Selected)
Register Name
Bit Name
Remarks
DVSTCTR RHST
FRMNUM
FRNM
The value is retained when the function controller
function is selected.
function is selected.
UFRMNUM
UFRNM
The value is retained when the function controller
function is selected.
function is selected.
26.3.2
CPU Bus Wait Setting Register (BUSWAIT)
BUSWAIT is a register that specifies the number of wait cycles to be inserted during an access
from the CPU to this module.
from the CPU to this module.
This register can be modified even when the SCKE bit in SYSCFG is 0.
This register is initialized by a power-on reset.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit:
Initial value:
R/W:
0
0
0
0
0
0
0
0
0
0
0
1
1
R
R
R
R
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
0
—
—
—
—
—
—
—
—
—
—
—
—
1
1
BWAIT[3:0]
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
15 to 4
All
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
should always be 0.
3 to 0
BWAIT[3:0]
1111
R/W
CPU Bus Access Wait
Specifies the number of wait cycles to be inserted
during an access to a register (the same number
applies to an access to a FIFO port). For details, see
section 26.4.1 (5), Register Access Wait Control.
during an access to a register (the same number
applies to an access to a FIFO port). For details, see
section 26.4.1 (5), Register Access Wait Control.
0000:
0 wait cycles (2 access cycles)
:
0010:
2 wait cycles (4 access cycles)
:
0100:
4 wait cycles (6 access cycles)
:
1111:
15 wait cycles (17 access cycles)