Renesas R5S72621 User Manual

 
Section 26   USB 2.0 Host/Function Module 

Page 1376 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

3 to 0 

CURPIPE[3:0]  0000 

R/W 

FIFO Port Access Pipe Specification 

Specifies the pipe number for reading or writing data 
through the D0FIFO/D1FIFO port.  

0000: No pipe specified 

0001: Pipe 1 

0010: Pipe 2 

0011: Pipe 3 

0100: Pipe 4 

0101: Pipe 5 

0110: Pipe 6 

0111: Pipe 7 

1000: Pipe 8 

1001: Pipe 9 

Other than above: Setting prohibited 

After writing to these bits, read these bits to check 
that the written value agrees with the read value 
before proceeding to the next process. 

Do not set the same pipe number to the CURPIPE 
bits in CFIFOSEL, D0FIFOSEL, and D1FIFOSEL. 

Even if an attempt is made to modify the setting of 
these bits during access to the FIFO buffer, the 
current access setting is retained until the access is 
completed. Then, the modification becomes effective 
thus enabling continuous access.  

Note:  *  Only 0 can be read and 1 can be written. 

 

CFIFOCTR, D0FIFOCTR and D1FIFOCTR are registers that determine whether or not writing to 
the buffer memory has been finished, the buffer accessed from the CPU has been cleared, and the 
FIFO port is accessible. CFIFOCTR, D0FIFOCTR, and D1FIFOCTR are used for the 
corresponding FIFO ports. 

These registers are initialized by a power-on reset.