Renesas R5S72621 User Manual

 

Section 26   USB 2.0 Host/Function Module 

R01UH0134EJ0400  Rev. 4.00  

 

Page 1389 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Bit:

Initial value:

R/W:

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

R

R

R

R

R

R

R

R/W

R

R/W

R

R

R

R

R

R

—

—

—

—

—

—

—

—

TRNEN

SEL

—

—

—

—

—

—

BRDYM

 

 

15 to 9 

 All 

0 

R 

Reserved 

These bits are always read as 0. The write value 
should always be 0. 

8 

TRNENSEL 

0 

R/W 

Transaction-Enabled Time Select 

Selects the transaction-enabled time either for full- or 
low-speed communication, during which this module 
issues tokens in a frame. 

0: For non-low-speed communication 

1: For low-speed communication 

This bit is valid only when the host controller function 
is selected. Even when the host controller function is 
selected, the setting of this bit has no effect on the 
transaction-enabled time during high-speed 
communication. 

This bit should be set to 0 when the function 
controller function is selected. 

7 

 0 

R 

Reserved 

This bit is always read as 0. The write value should 
always be 0. 

6 

BRDYM 

0 

R/W 

BRDY Interrupt Status Clear Timing for each Pipe 

Specifies the timing for clearing the BRDY interrupt 
status for each pipe. 

Set the BRDYM bit during the initial settings of the 
USB 2.0 host/function module (before performing 
data communication). Do not change the setting of 
the BRDYM bit after data communication starts. 

0: Writing 0 clears the status. 

1: This module automatically clears the status when 

data has been read from the FIFO buffer or data 
has been written to the FIFO buffer. 

5 to 0 

 All 

0 

R 

Reserved 

These bits are always read as 0. The write value 
should always be 0.