Renesas R5S72621 User Manual
Section 26 USB 2.0 Host/Function Module
R01UH0134EJ0400 Rev. 4.00
Page 1395 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Notes: 1. This bit is initialized to B'0 by a power-on reset and B'1 by a USB bus reset.
2. These bits are initialized to B'000 by a power-on reset and B'001 by a USB bus reset.
3. This bit is initialized to 0 when the level of the VBUS pin input is high and 1 when low.
4. To clear the VBINT, RESM, SOFR, DVST, or CTRT bit, write 0 only to the bits to be
cleared; write 1 to the other bits. Do not write 0 to the status bits indicating 0.
5. This module can detect a change in the status indicated by the VBINT and RESM bits
even while the clock supply is stopped (while SCKE is 0), and outputs interrupts when
the corresponding interrupt enable bits are enabled. Clearing the status should be done
after enabling the clock supply.
the corresponding interrupt enable bits are enabled. Clearing the status should be done
after enabling the clock supply.
6. A change in the status of the RESM, DVST, and CTRT bits occur only when the
function controller function is selected; disable the corresponding interrupt enable bits
(set to 0) when the host controller function is selected.
(set to 0) when the host controller function is selected.
7. Only 0 can be written.
26.3.17
Interrupt Status Register 1 (INTSTS1)
INTSTS1 is a register that is used to confirm interrupt status.
The various interrupts indicated by the bits in this register should be enabled only when the host
controller function is selected.
controller function is selected.
This register is initialized by a power-on reset.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit:
Initial value:
R/W:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R/W*
1
R
R/W*
1
R/W*
1
R
R
R
R
R/W*
1
R/W*
1
R/W*
1
R
R
R
R
—
BCHG
—
DTCH ATTCH
—
—
—
—
EOF
ERR
ERR
SIGN
SACK
—
—
—
—
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
15
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
always be 0.