Renesas R5S72621 User Manual

Page of 2152
 
Section 26   USB 2.0 Host/Function Module 
R01UH0134EJ0400  Rev. 4.00  
 
Page 1401 of 2108 
Sep 24, 2014 
 
 
 
SH7262 Group, SH7264 Group 
Bit Bit 
Name 
Initial 
Value R/W Description 
4 SACK  0  R/W*
1
Setup Transaction Normal Response Interrupt Status 
Indicates the status of the setup transaction normal 
response interrupt when the host controller function 
is selected. 
0: SACK interrupts not generated 
1: SACK interrupts generated 
This module detects the SACK interrupt when ACK 
response is returned from the peripheral device 
during the setup transactions issued by this module, 
and sets this bit to 1. Here, if the corresponding 
interrupt enable bit has been set to 1, this module 
generates the SACK interrupt. 
3 to 0 
 All 
Reserved 
These bits are always read as 0. The write value 
should always be 0. 
Notes:  1.  Only 0 can be written. 
 
2.  This module can detect a change in the status indicated by the BCHG bit even while the 
clock supply is stopped (while SCKE is 0), and outputs an interrupt when the 
corresponding interrupt enable bit is enabled. Clearing the status should be done after 
enabling the clock supply.  
No interrupts other than BCHG can be detected while the clock supply is stopped (while 
SCKE is 0). 
 
26.3.18
  BRDY Interrupt Status Register (BRDYSTS) 
BRDYSTS is a register that indicates the BRDY interrupt status for each pipe. 
This register is initialized by a power-on reset. 
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit:
Initial value:
R/W:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R/W*
1
R/W*
1
R/W*
1
R/W*
1
R/W*
1
R/W*
1
R/W*
1
R/W*
1
R/W*
1
R/W*
1
PIPE9
BRDY
PIPE8
BRDY
PIPE7
BRDY
PIPE6
BRDY
PIPE5
BRDY
PIPE4
BRDY
PIPE3
BRDY
PIPE2
BRDY
PIPE1
BRDY
PIPE0
BRDY