Renesas R5S72621 User Manual

Page of 2152
 
Section 26   USB 2.0 Host/Function Module 
Page 1472 of 2108 
 
R01UH0134EJ0400  Rev. 4.00 
 
 Sep 
24, 
2014 
SH7262 Group, SH7264 Group
26.4
 
Operation 
26.4.1
 
System Control and Oscillation Control 
This section describes the register operations that are necessary to the initial settings of this 
module, and the registers necessary for power consumption control. 
(1)  Resets 
Table 26.15 lists the types of controller resets. For the initialized states of the registers following 
the reset operations, see section 26.3, Register Description. 
Table 26.15  Types of Reset 
Name Operation 
Power-on reset 
Low level input from the 
RES pin  
USB bus reset 
Automatically detected by this module from the D
 and D lines when the 
function controller function is selected 
 
(2)  Controller Function Selection 
This module can select the host controller function or function controller function using the 
DCFM bit in SYSCFG. Changing the DCFM bit should be done in the initial settings immediately 
after a power-on reset or in the D+ pull-up disabled (DPRPU = 0) and D + /D 
 pull-down 
disabled (DRPD = 0) state. 
(3)  Enabling High-Speed Operation 
This module can select a USB communication speed (communication bit rate). When the host 
controller function is selected, the high-speed operation or full-speed/low-speed operation can be 
set. When the function controller function is selected, either the high-speed operation or full-speed 
operation can be selected. In order to enable the high-speed operation for this module, the HSE bit 
in SYSCFG should be set to 1. If high-speed mode has been enabled, this module executes the 
reset handshake protocol, and the USB communication speed is set automatically. The results of 
the reset handshake can be confirmed using the RHST bit in DVSTCTR.  
If high-speed operation has been disabled, this module operates at full-speed or low-speed. If the 
function controller function is also selected, this module operates at full-speed. 
Changing the HSE bit should be done between the ATTCH interrupt detection and bus reset 
execution when the host controller function is selected, or with the D+ line pull-up disabled 
(DPRPU = 0) when the host controller function is selected.