Renesas R5S72621 User Manual
Section 26 USB 2.0 Host/Function Module
R01UH0134EJ0400 Rev. 4.00
Page 1539 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Interval counter started
USB bus
PID bit setting
NAK
S
O
F
S
O
F
S
O
F
S
O
F
S
O
F
S
O
F
S
O
F
BUF
BUF
BUF
BUF
BUF
BUF
Token
reception
is waited
Token
reception
is waited
D
A
T
A
0
D
A
T
A
0
D
A
T
A
0
O
U
T
O
U
T
O
U
T
Token
reception
is waited
Token
reception
is not waited
Token
reception
is not waited
Token
reception
is not waited
Token
reception
is not waited
Token
Figure 26.19 Relationship between (
) Frames and Expected Token Reception
when IITV = 1
When the selected pipe is for isochronous IN transfers
The IFIS bit should be 1 for this use. When IFIS = 0, this module transmits a data packet in
response to the received IN token irrespective of the IITV bit setting.
response to the received IN token irrespective of the IITV bit setting.
When IFIS = 1, this module clears the FIFO buffer when this module fails to receive an IN
token within the interval set by the IITV bits in terms of (
token within the interval set by the IITV bits in terms of (
) frames in a state in which there is
data to be transmitted in the FIFO buffer.
This module also clears the FIFO buffer when this module fails to receive an IN token
successfully because of a bus error such as a CRC error contained in the token.
successfully because of a bus error such as a CRC error contained in the token.
This module clears the FIFO buffer on receiving an SOF packet. Even if the SOF packet is
corrupted, the internal interpolation is used and allows the FIFO buffer to be cleared at the
timing to receive the SOF packet.
corrupted, the internal interpolation is used and allows the FIFO buffer to be cleared at the
timing to receive the SOF packet.
The interval counting starts at the different timing depending on the IITV bit setting (similar to
the timing during OUT transfers).
the timing during OUT transfers).
The interval count clearing condition is any of the following in function controller mode.
When a power-on reset is applied.
When the ACLRM bit is set to 1.
When this module detects a USB bus reset.