Renesas R5S72621 User Manual

 

Section 27   Video Display Controller 3 

R01UH0134EJ0400  Rev. 4.00  

 

Page 1547 of 2108 

Sep 24, 2014 

 

 

 
SH7262 Group, SH7264 Group 

Section 27   Video Display Controller 3 

The video display controller 3 provides the following four functions. Note that the video display 
function and video recording function cannot be used together. 

1.  Video display function: Reduces the size of the input video, buffers the resultant video data in 

the memory, and then displays the video on the panel. 

2.  Video recording function: Stores a specified number of input video fields in on-chip large-

capacity RAM or SDRAM. 

3.  Function for overlaying graphics images (two planes) on the input video. 

4.  Function for outputting the control signals for the TFT-LCD panel. 
 

Operating frequency 

Video input clock: 27 MHz 

Panel clock: 4 MHz to 36 MHz (depends on the panel specifications)  

Input video standard 

8-bit input conforming to the ITU-R BT.656 standard (27 MHz)  

8-bit serial input conforming to the ITU-R BT.601 standard (27 MHz)  

Video recording 
function 

Stores video data in the RGB565 format at a rate of 1/2 field  
(NTSC: 30 fps; PAL: 25 fps). 

Video quality 
adjustment function 

Contrast adjustment and brightness adjustment 

Video scaling 
processing 

Vertical: 

1/2, 1/3, or 1/4 

Horizontal: 

2/3, 1/2, 1/3, or 1/4 

For the support of PAL, each scaled value can be further multiplied by 6/7.

Graphics images 

Two planes (layers 1 and 2) 

RGB565 progressive format  
(R = 5 bits, G = 6 bits, and B = 5 bits; 16 bits in total) 
RGB4444 progressive format  
(

 = 4 bits, R = 4 bits, G = 4 bits, and B = 4 bits; 16 bits in total)