Renesas R5S72621 User Manual
Section 27 Video Display Controller 3
Page 1572 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W
Value R/W
Description
4 VIDEO_MODE
0
R/W
Specifies
the operating mode for the video
receiving block.
0: Video recording mode
(Be sure to set the EX_SYNC_MODE bit in the
SGMODE register to 0)
SGMODE register to 0)
1: Video display mode
(Be sure to set the EX_SYNC_MODE bit in the
SGMODE register to 1)
SGMODE register to 1)
3, 2
All
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
should always be 0.
1 VIDEO_DISP_
EXE
0
R/W
Enables the video supplying block operation.
Setting to 1 starts video supply to the graphics
blocks. The register setting is updated with the
VSYNC timing.
Setting to 1 starts video supply to the graphics
blocks. The register setting is updated with the
VSYNC timing.
0: Disabled
1: Enabled
0 VIDEO_MAIN_
EXE
0
R/W
Enables the video receiving block operation.
Setting to 1 starts video storing in the large-
capacity on-chip RAM or SDRAM.
Setting to 1 starts video storing in the large-
capacity on-chip RAM or SDRAM.
0: Disabled*
2
1: Enabled
Notes: 1. Operation of the video receiving and supplying blocks proceeds after bit
VIDEO_DISP_EXE or VIDEO_MAIN_EXE, respectively, is set to 1, and detection of
VSYCN. Operation stops when the protocol for the internal bus is ended after the
corresponding bit has been cleared to 0.
VSYCN. Operation stops when the protocol for the internal bus is ended after the
corresponding bit has been cleared to 0.
2. To disable the video receiving block operation, please follow the procedure shown in
section 27.10.1, The Procedure of Disabling the Video Receiving Block Operation.