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Renesas R5S72621 User Manual

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Section 27   Video Display Controller 3 
Page 1584 of 2108 
 
R01UH0134EJ0400  Rev. 4.00 
 
 Sep 
24, 
2014 
SH7262 Group, SH7264 Group
27.7.8
 
Video Storing Field Count Register (VIDEO_SAVE_NUM) 
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
-
-
-
-
-
-
FIELD_NUM[9:0]
FIELD_SAVE_NUM[9:0]
-
-
-
-
-
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
 
 
Bit Bit 
Name 
Initial 
Value R/W  Description 
31 to 26 
 All 
0 
R 
Reserved 
These bits are always read as 0. The write value 
should always be 0. 
25 to 16 
FIELD_NUM 
[9:0] 
H'000 
R 
These bits indicate the field number of which 
recording processing has been completed in the 
video recording mode. These bits are cleared to 
H'000 when the VIDEO_MAIN_EXE bit in the 
VIDEO_MODE register is cleared to 0. 
15 to 10 
 All 
0 
R 
Reserved 
These bits are always read as 0. The write value 
should always be 0. 
9 to 0 
FIELD_SAVE_ 
NUM [9:0] 
H'000 
R/W 
These bits specify the number of fields to be 
stored. Set these bits to H'000 in the video display 
mode (when the VIDEO_MODE bit in the 
VIDEO_MODE register is set to 1). 
H'000: One field is stored. 
H'001: Two fields are stored. 
H'03B: 60 fields are stored. 
H'3FF: 1024 fields are stored. 
Note:  After data has been written for the specified number of fields, the memory is overwritten by 
new video data from the first address. 
 
Video data is stored at a 1/2-field rate (NTSC: 30 fps; PAL: 25 fps). 
 
When the VIDEO_MAIN_EXE bit in the VIDEO_MODE register is cleared to 0, the address 
calculation result is initialized and data is written to the initial field storing area.