Manualsbrain.com
  1. Manuals
  2. Brands
  3. Renesas
  4. R5S72621
  5. User Manual

Renesas R5S72621 User Manual

Download
Page of 2152
 
Section 27   Video Display Controller 3 
Page 1612 of 2108 
 
R01UH0134EJ0400  Rev. 4.00 
 
 Sep 
24, 
2014 
SH7262 Group, SH7264 Group
27.7.30
  Interrupt Output Control Register (SGINTCNT) 
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R/W*
2
-
-
-
INT_LINE_NUM[9:0]
-
-
-
INT_LINE_
EN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LINE_
STATUS
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
 
 
Bit Bit 
Name 
Initial 
Value R/W Description 
31, 30 
 All 
0 
R 
Reserved 
These bits are always read as 0. The write value 
should always be 0. 
29 to 20 
INT_LINE_
NUM[9:0] 
All 0 
R/W 
These bits specify the line number for which a line 
interrupt is to be output. 
19 to 17 
 All 
0 
R 
Reserved 
These bits are always read as 0. The write value 
should always be 0. 
16 INT_LINE_ 
EN 
0 
R/W 
Enables output of line interrupts. 
0: Disabled 
1: Enabled 
15 to 1 
 All 
0 
R 
Reserved 
These bits are always read as 0. The write value 
should always be 0. 
0 LINE_ 
STATUS 
0 R/W*
2
 
Indicates the line interrupt status.*
1
 
0: No interrupt has occurred. 
1: An interrupt has occurred. 
Notes:  1.  The status bit (bit 0) always operates regardless of the operation enabling bit setting. 
After being set to 1, the status bit remains at 1 until cleared 0. 
 
2.  Only 0 can be written.