Renesas R5S72621 User Manual
Section 28 Sampling Rate Converter
R01UH0134EJ0400 Rev. 4.00
Page 1641 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Table 28.4 Alignment of Data before Sampling Rate Conversion (Channel 1)
IED
Upper Byte
Lower Byte
0 SRCID[15:8]
SRCID[7:0]
1 SRCID[7:0]
SRCID[15:8]
28.2.2
Output Data Register (SRCOD)
SRCOD is a 32-bit read-only register used to output the data after sampling rate conversion. The
data in the output data FIFO is read through SRCOD. When the number of data in the output data
FIFO is zero after the start of conversion, the value previously read is read again.
data in the output data FIFO is read through SRCOD. When the number of data in the output data
FIFO is zero after the start of conversion, the value previously read is read again.
(1) Output Data Register_0 (SRCOD_0)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit:
Initial value:
R/W:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
(2) Output Data Register_1 (SRCOD_1)
The conversion result is stored in bits 31 to 16. Bits 15 to 0 are always read as 0.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit:
Initial value:
R/W:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R