Renesas R5S72621 User Manual
Section 28 Sampling Rate Converter
R01UH0134EJ0400 Rev. 4.00
Page 1653 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
28.2.6
Status Register (SRCSTAT)
SRCSTAT is a 16-bit readable/writable register that indicates the number of data units in the input
and output data FIFOs, whether the various interrupt sources have been generated or not, and the
flush processing status.
and output data FIFOs, whether the various interrupt sources have been generated or not, and the
flush processing status.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit:
Initial value:
R/W:
0
0
0
0
0
0
1
0
R
R
R(W)*
1
R
R(W)*
1
R/(W)*
1
R/(W)*
1
R/(W)*
1
Note:
Only 0 can be written after having read as 1.
*
1
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
OFDN[4:0]
IFDN[3:0]
⎯
CEF
FLF
UDF
OVF
IINT
OINT
Bit Bit
Name
Initial
Value
Value
R/W Description
15 to 11 OFDN[4:0]
All 0
R
Output FIFO Data Count
Indicates the number of data units in the output FIFO.
Note: For channel 1, bits 15 and 14 are reserved
and always read as 0. The write value should
always be 0.
always be 0.
10 to 7
IFDN[3:0]
All 0
R
Input FIFO Data Count
Indicates the number of data units in the input FIFO.
6
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
always be 0.
5 CEF 0 R/(W)*
1
Conversion End Flag
Indicates that all the output data is read after flush
processing is completed.
processing is completed.
[Clearing conditions]
When 0 has been written to the CEF bit after
reading CEF = 1.
When 1 has been written to the CL bit in
SRCCTRL.
When 1 has been written to the SRCEN bit in
SRCCTRL while SRCEN is 0.
[Setting condition]
When the number of data units in the output data
FIFO is zero on completion of flush processing.