Renesas R5S72621 User Manual

 
Section 28   Sampling Rate Converter 

Page 1664 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

After the following write access to SRCCTRL, three cycles of the peripheral clock (P

) elapse 

before the corresponding bit in SRCSTAT is updated.  

  Before the FLF bit in SRCSTAT is set after 1 is written to the FL bit in SRCCTRL  
  Before each bit in SRCSTAT is initialized after 1 is written to the CL bit in SRCCTRL  
  Before each bit in SRCSTAT is initialized after 1 is written to the SRCEN bit in SRCCTRL 

while the SRCEN bit is 0 

 
On the other hand, as the CPU executes any subsequent instruction without waiting for the 
completion of the register writing, an instruction that immediately follows that used to write to 
SRCCTRL cannot accurately detect the updated state of SRCSTAT. To check the updated 
SRCSTAT state, dummy-read SRCCTRL or SRCSTAT after the instruction used to write to 
SRCCTRL. 

When 1 is written to the FL bit in SRCCTRL, this module continues conversion processing by 
adding 0-data to the input data end point. Flush processing, therefore, should be performed when 
the audio data end point is input and there is no subsequent data. 

To perform conversion again after flush processing, clear the internal work memory in either of 
the following ways. 

  Write 1 to the CL bit in SRCCTRL. 
  Write 0 and then 1 to the SRCEN bit in SRCCTRL.