Renesas R5S72621 User Manual
Section 6 Exception Handling
Page 138 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Type
Conditions for Transition to Reset State
Internal States
RES
User Debugging
Interface Command
Watchdog
Timer
Overflow CPU
Other
Modules
On-Chip
High-Speed
RAM
On-Chip Large-
Capacity RAM
(Excluding
On-Chip Data
Retention RAM)
On-Chip
Data
Retention
RAM
Manual
reset
High Command
other
than
user debugging
interface reset assert is
set
Manual
reset
Initialized *
1
Retained
contents
Retained contents
Retained
contents
Notes: 1. See section 36.3, Register States in Each Operating Mode.
2. Data are retained when the setting of either the RAME or RAMWE bit is disabled.
3. Data are retained when the setting of either the VRAME or VRAMWE bit is disabled.
4. Data are retained when the setting of any of the VRAME, VRAMWE, or RRAMWE bits
is disabled.
5. When the deep standby mode is canceled by a power-on reset, the data cannot be
retained.