Renesas R5S72621 User Manual

Renesas

Section 33 Power-Down Modes

Page 1770 of 2108

R01UH0134EJ0400 Rev. 4.00

Sep

24,

2014

SH7262 Group, SH7264 Group

Table 33.1 States of Power-Down Modes

State*

1

Power-

Down

Mode

Transition

Conditions

Clock

Pulse

Genera-

tor

CPU

CPU

Register

High-

Speed

On-Chip

RAM

Cash

Memory

Large-

Capacity

On-Chip

RAM

(for Data

Retention)

On-Chip

Peripheral

Modules

Realtime

Clock

Power

supply

External

Memory

Canceling

Procedure

Sleep

mode

Execute

SLEEP

instruction

with STBY bit

in STBCR

cleared to 0

Running

Halted Held

Running

Running Running Running*

2

Running Auto-

refresh



Interrupt



Manual reset



Power-on

reset



DMA address

error

Software

standby

mode

Execute

SLEEP

instruction

with STBY bit

in STBCR set

to 1 and

DEEP bit to 0

Halted Halted Held

Halted

(contents

are

held *

5

*

6

)

Halted

(contents

are

held *

5

*

7

)

Halted Running*

2

Running Self-

refresh



NMI interrupt



IRQ interrupt



Power-on

reset

Deep

standby

mode

Execute

SLEEP

instruction

with STBY

and DEEP

bits in STBCR

set to 1

Halted Halted Halted Halted

(contents

are not

held)

Halted

(contents

in on-chip

data-

retention

RAM are

held*

3

)

Halted Running*

2

Halted

Self-

refresh



NMI interrupt*

4



Power-on

reset*

4



Realtime clock

alarm

interrupt*

4



Change on the

pins for

canceling*

4