Renesas R5S72621 User Manual
Section 33 Power-Down Modes
R01UH0134EJ0400 Rev. 4.00
Page 1811 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
33.3.4
Deep Standby Mode
(1) Transition to Deep Standby Mode
The LSI switches from a program execution state to deep standby mode by executing the SLEEP
instruction when the STBY bit and DEEP bit in STBCR1 are set to 1. In deep standby mode, not
only the CPU, clocks, and on-chip peripheral modules but also power supply is turned off
excluding the on-chip data-retention RAM area specified by the RRAMKP3 to RRAMKP0 bits in
RRAMKP and realtime clock. This can significantly reduce power consumption. Therefore, data
in the registers of the CPU, cache, and on-chip peripheral modules are not retained. Pin state
values immediately before the transition to deep standby mode are retained.
instruction when the STBY bit and DEEP bit in STBCR1 are set to 1. In deep standby mode, not
only the CPU, clocks, and on-chip peripheral modules but also power supply is turned off
excluding the on-chip data-retention RAM area specified by the RRAMKP3 to RRAMKP0 bits in
RRAMKP and realtime clock. This can significantly reduce power consumption. Therefore, data
in the registers of the CPU, cache, and on-chip peripheral modules are not retained. Pin state
values immediately before the transition to deep standby mode are retained.
The CPU takes one cycle to finish writing to DSFR, and then executes processing for the next
instruction. However, it actually takes one or more cycles to write. Therefore, execute a SLEEP
instruction after reading DSFR to reflect the values written to DSFR by the CPU in the SLEEP
instruction without fail.
instruction. However, it actually takes one or more cycles to write. Therefore, execute a SLEEP
instruction after reading DSFR to reflect the values written to DSFR by the CPU in the SLEEP
instruction without fail.
The procedure for switching to deep standby mode is as follows. Figure 33.2 also shows its
flowchart.
flowchart.
1. Set the RRAMKP3 to RRAMKP0 bits in RRAMKP for the corresponding on-chip data-
retention RAM area that must be retained. Transfer the programs to be retained to the specified
areas of the on-chip data-retention RAM.
areas of the on-chip data-retention RAM.
2. Set the RAMBOOT and EBUSKEEPE bits in DSCTR to specify the activation method for
returning from deep standby mode and to select whether the external memory control pin
status is retained or not.
status is retained or not.
3. When canceling deep standby mode by an interrupt, set the corresponding bit in DSSSR to
select the pin or source to cancel deep standby mode. In this case, specify the input signal
detection mode for the selected pin with the corresponding bit in DSESR.
detection mode for the selected pin with the corresponding bit in DSESR.
4. Execute read and write of an arbitrary but the same address for each page in the on-chip data-
retention RAM area. When this is not executed, data last written may not be written to the on-
chip data-retention RAM. If there is a write to the on-chip data-retention RAM after this time,
execute this processing after the last write to the on-chip data-retention RAM.
chip data-retention RAM. If there is a write to the on-chip data-retention RAM after this time,
execute this processing after the last write to the on-chip data-retention RAM.
5. Set the STBY and DEEP bits in STBCR1 to 1.
6. Read out the DSFR register after clearing the flag in the DSFR register. Then execute the
SLEEP instruction.