Renesas R5S72621 User Manual
Section 6 Exception Handling
Page 150 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
6.6.6
FPU Exceptions
An FPU exception handling is generated when the V, Z, O, U or I bit in the FPU exception enable
field (Enable) of the floating point status/control register (FPSCR) is set. This indicates the
occurrence of an invalid operation exception defined by the IEEE standard 754, a division-by-zero
exception, overflow (in the case of an instruction for which this is possible), underflow (in the
case of an instruction for which this is possible), or inexact exception (in the case of an instruction
for which this is possible).
field (Enable) of the floating point status/control register (FPSCR) is set. This indicates the
occurrence of an invalid operation exception defined by the IEEE standard 754, a division-by-zero
exception, overflow (in the case of an instruction for which this is possible), underflow (in the
case of an instruction for which this is possible), or inexact exception (in the case of an instruction
for which this is possible).
The floating point operation instructions that may cause an FPU exception handling are FADD,
FSUB, FMUL, FDIV, FMAC, FCMP/EQ, FCMP/GT, FLOAT, FTRC, FCNVDS, FCNVSD, and
FSQRT.
FSUB, FMUL, FDIV, FMAC, FCMP/EQ, FCMP/GT, FLOAT, FTRC, FCNVDS, FCNVSD, and
FSQRT.
An FPU exception handling is generated only when the corresponding FPU exception enable bit
(Enable) is set. When the FPU detects an exception source in floating point operation, FPU
operation is halted and generation of an FPU exception handling is reported to the CPU. When
exception handling is started, the CPU operations are as follows.
(Enable) is set. When the FPU detects an exception source in floating point operation, FPU
operation is halted and generation of an FPU exception handling is reported to the CPU. When
exception handling is started, the CPU operations are as follows.
1. The start address of the exception service routine which corresponds to the FPU exception
handling that occurred is fetched from the exception handling vector table.
2. The status register (SR) is saved to the stack.
3. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
instruction to be executed after the last executed instruction.
4. After jumping to the exception service routine start address fetched from the exception
handling vector table, program execution starts. This jump is not a delayed branch.
The FPU exception flag field (Flag) of FPSCR is always updated regardless of whether or not an
FPU exception handling has been accepted, and remains set until explicitly cleared by the user
through an instruction. The FPU exception source field (Cause) of FPSCR changes each time a
floating point operation instruction is executed.
When the V bit in the FPU exception enable field (Enable) of FPSCR is set and the QIS bit in
FPSCR is also set, FPU exception handling is generated when qNAN or
FPSCR is also set, FPU exception handling is generated when qNAN or
is input to a floating
point operation instruction source.