Renesas R5S72621 User Manual

 
Section 6   Exception Handling 
 

Page 154 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

Before exception handling begins running, the exception handling vector table must be stored in a 
memory, and the CPU must be able to access the memory. So, if the exception handling is 
generated 

  Ex. 1:  when the exception handling vector table is stored in an external address space, but the  

 

settings of bus state controller and general I/O ports to access the external address space  

 

have been not completed yet, or 

  Ex. 2: when the exception handling vector table is stored in the on-chip RAM, but the vector  

 

base register (VBR) has been not changed to the on-chip RAM address yet, 

the CPU fetches an unintended value as the execution start address, and starts executing programs 
from unintended address. 

Before the settings necessary to access the external CS0 space are completed, the manual reset 
should not be generated. When a manual reset is issued, the CPU fetches the program execution 
start address from the manual reset vector table address offset (H'00000008), which is to say 
always from the external CS0 space. Additionally, in the case that no memory is connected to the 
external CS0 space in boot mode 1 to 3, the manual reset should not be generated. 

Before the exception handling vector table is stored in a memory and the settings necessary to 
access the memory are completed, the NMI interrupt should not be generated. (Do not enable 
interrupts on the 640 KB version.) 

Specially in boot mode 1 to 3, the VBR is kept as the initial value H'00000000 in the period of the 
boot operation (before the transfer of the loader program is completed and the CPU jumps to the 
on-chip high-speed RAM). Before the VBR is changed or the settings necessary to access the 
external address space are completed in the loader program, the NMI interrupt should not be 
generated. (Do not enable interrupts on the 640 KB version.) 

Before the exception handling vector table is stored in a memory and the settings necessary to 
access the memory are completed, the settings to permit the interrupts should not be done.