Renesas R5S72621 User Manual
Section 7 Interrupt Controller
R01UH0134EJ0400 Rev. 4.00
Page 157 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Section 7 Interrupt Controller
The interrupt controller ascertains the priority of interrupt sources and controls interrupt requests
to the CPU. The interrupt controller registers set the order of priority of each interrupt, allowing
the user to process interrupt requests according to the user-set priority.
to the CPU. The interrupt controller registers set the order of priority of each interrupt, allowing
the user to process interrupt requests according to the user-set priority.
7.1
Features
16 levels of interrupt priority can be set.
By setting the twenty interrupt priority registers, the priorities of IRQ interrupts, PINT
interrupts, and on-chip peripheral module interrupts can be selected from 16 levels for request
sources.
interrupts, and on-chip peripheral module interrupts can be selected from 16 levels for request
sources.
NMI noise canceler function
An NMI input-level bit indicates the NMI pin state. By reading this bit in the interrupt
exception service routine, the pin state can be checked, enabling it to be used as the noise
canceler function.
exception service routine, the pin state can be checked, enabling it to be used as the noise
canceler function.
Register banks
This LSI has register banks that enable register saving and restoration required in the interrupt
processing to be performed at high speed.
processing to be performed at high speed.