Renesas R5S72621 User Manual
R01UH0134EJ0400 Rev. 4.00
Page 2097 of 2108
Sep 24, 2014
Index
Numerics
(Potential) time master .......................... 1065
16-bit/32-bit displacement ........................ 59
16-bit/32-bit displacement ........................ 59
A
A/D conversion time
(multi mode and scan mode) ................. 1278
A/D conversion time (single mode) ...... 1278
A/D conversion timing ......................... 1277
A/D converter ....................................... 1259
A/D converter activation ......................... 585
A/D converter characteristics................ 2046
A/D converter start request delaying
function ................................................... 578
A/D converter timing ............................ 2029
Absolute address ....................................... 59
Absolute address accessing ....................... 59
Absolute maximum ratings ................... 1961
AC characteristics ................................. 1974
AC characteristics measurement
conditions ............................................. 2045
Access size and data alignment .............. 291
Access wait control ................................. 298
Address array .................................. 210, 224
Address array read .................................. 224
Address errors ......................................... 142
Address map ........................................... 234
Address multiplexing .............................. 307
Address spaces of on-chip data
retention RAM ...................................... 1672
Address spaces of on-chip
high-speed RAM ................................... 1671
Address spaces of on-chip large
capacity RAM ....................................... 1672
Address-array write
(associative operation) ............................ 225
(multi mode and scan mode) ................. 1278
A/D conversion time (single mode) ...... 1278
A/D conversion timing ......................... 1277
A/D converter ....................................... 1259
A/D converter activation ......................... 585
A/D converter characteristics................ 2046
A/D converter start request delaying
function ................................................... 578
A/D converter timing ............................ 2029
Absolute address ....................................... 59
Absolute address accessing ....................... 59
Absolute maximum ratings ................... 1961
AC characteristics ................................. 1974
AC characteristics measurement
conditions ............................................. 2045
Access size and data alignment .............. 291
Access wait control ................................. 298
Address array .................................. 210, 224
Address array read .................................. 224
Address errors ......................................... 142
Address map ........................................... 234
Address multiplexing .............................. 307
Address spaces of on-chip data
retention RAM ...................................... 1672
Address spaces of on-chip
high-speed RAM ................................... 1671
Address spaces of on-chip large
capacity RAM ....................................... 1672
Address-array write
(associative operation) ............................ 225
Addressing modes ..................................... 60
Analog input pin ratings ........................ 1284
Arithmetic operation instructions .............. 79
Automatic decoding stop function ........ 1249
Auto-refreshing ....................................... 329
Auto-request mode .................................. 410
Analog input pin ratings ........................ 1284
Arithmetic operation instructions .............. 79
Automatic decoding stop function ........ 1249
Auto-refreshing ....................................... 329
Auto-request mode .................................. 410
B
Bank active ............................................. 322
Banked register and input/
output of banks ........................................ 202
Baud rate generator ................................. 963
Bit manipulation instructions .................... 90
Bit synchronous circuit ........................... 887
Block diagram of this LSI ......................... 14
Boot mode ............................................... 109
Branch instructions ................................... 84
Break detection and processing ............... 772
Buffering format ................................... 1250
Burst mode .............................................. 423
Burst read ................................................ 314
Burst ROM (clocked asynchronous)
interface .................................................. 342
Burst ROM (clocked synchronous)
interface .................................................. 355
Burst write ............................................... 319
Bus arbitration ......................................... 364
Bus state controller ................................. 229
Bus timing ............................................. 1981
Bus-released state ...................................... 93
Banked register and input/
output of banks ........................................ 202
Baud rate generator ................................. 963
Bit manipulation instructions .................... 90
Bit synchronous circuit ........................... 887
Block diagram of this LSI ......................... 14
Boot mode ............................................... 109
Branch instructions ................................... 84
Break detection and processing ............... 772
Buffering format ................................... 1250
Burst mode .............................................. 423
Burst read ................................................ 314
Burst ROM (clocked asynchronous)
interface .................................................. 342
Burst ROM (clocked synchronous)
interface .................................................. 355
Burst write ............................................... 319
Bus arbitration ......................................... 364
Bus state controller ................................. 229
Bus timing ............................................. 1981
Bus-released state ...................................... 93
C
Cache ...................................................... 209
Cache operations ..................................... 222
Cache operations ..................................... 222