Renesas R5S72621 User Manual
Section 9 Bus State Controller
R01UH0134EJ0400 Rev. 4.00
Page 239 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
9.4.1
Common Control Register (CMNCR)
CMNCR is a 32-bit register that controls the common items for each area.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R/W
R/W
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
BLOCK
DPRTY[1:0]
DMAIW[2:0]
DMA
IWA
-
-
-
HIZ
MEM
HIZ
CNT*
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
31 to 13
All
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
should always be 0.
12
1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
always be 1.
11 BLOCK
0 R/W
Bus
Lock
Specifies whether or not the
BREQ signal is received.
0: Receives
BREQ.
1: Does not receive
BREQ.