Renesas R5S72621 User Manual

 
Section 9   Bus State Controller 
 

Page 342 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

The burst ROM (clocked asynchronous) interface is used to access a memory with a high-speed 
read function using a method of address switching called the burst mode or page mode. In a burst 
ROM (clocked asynchronous) interface, basically the same access as the normal space is 
performed, but the 2nd and subsequent access cycles are performed only by changing the address, 
without negating the 

RD signal at the end of the 1st cycle. In the 2nd and subsequent access 

cycles, addresses are changed at the falling edge of the CKIO. 

For the 1st access cycle, the number of wait cycles specified by the W3 to W0 bits in CSnWCR is 
inserted. For the 2nd and subsequent access cycles, the number of wait cycles specified by the 
BW1 and BW0 bits in CSnWCR is inserted. 

In the access to the burst ROM (clocked asynchronous), the 

BS signal is asserted only to the first 

access cycle. An external wait input is valid only to the first access cycle. 

In the single access or write access that does not perform the burst operation in the burst ROM 
(clocked asynchronous) interface, access timing is same as a normal space.  

Table 9.15 lists a relationship between bus width, access size, and the number of bursts. Figure 
9.33 shows a timing chart.  

8 bits 

8 bits 

Not affected 

1 

1 

 

16 bits 

Not affected 

2 

1 

 

32 bits 

Not affected 

4 

1 

 16 

bytes 

00 

16 

1 

  

01 

4 

4