Renesas R5S72621 User Manual
Section 9 Bus State Controller
Page 366 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
CKIO
Other bus
control signals
BREQ
BACK
A25 to A0
D15 to D0
D15 to D0
CSn
Figure 9.47 Bus Arbitration Timing
9.5.13
Others
(1) Reset
This module can be initialized completely only at power-on reset. At power-on reset, all signals
are negated and data output buffers are turned off regardless of the bus cycle state after the internal
reset is synchronized with the internal clock. All control registers are initialized. In software
standby, sleep, and manual reset, control registers of the bus state controller are not initialized. At
manual reset, only the current bus cycle being executed is completed. Since the RTCNT continues
counting up during manual reset signal assertion, a refresh request occurs to initiate the refresh
cycle.
are negated and data output buffers are turned off regardless of the bus cycle state after the internal
reset is synchronized with the internal clock. All control registers are initialized. In software
standby, sleep, and manual reset, control registers of the bus state controller are not initialized. At
manual reset, only the current bus cycle being executed is completed. Since the RTCNT continues
counting up during manual reset signal assertion, a refresh request occurs to initiate the refresh
cycle.
(2) Access from the Side of the LSI Internal Bus Master
There are three types of LSI internal buses: a CPU bus, internal bus, and peripheral bus. The CPU
and cache memory are connected to the CPU bus. The bus state controller and internal bus masters
other than the CPU are connected to the internal bus. Low-speed peripheral modules are connected
to the peripheral bus. Internal memories other than the cache memory are connected
bidirectionally to the CPU bus and internal bus. Access from the CPU bus to the internal bus is
enabled but access from the internal bus to the CPU bus is disabled. This gives rise to the
following problems.
and cache memory are connected to the CPU bus. The bus state controller and internal bus masters
other than the CPU are connected to the internal bus. Low-speed peripheral modules are connected
to the peripheral bus. Internal memories other than the cache memory are connected
bidirectionally to the CPU bus and internal bus. Access from the CPU bus to the internal bus is
enabled but access from the internal bus to the CPU bus is disabled. This gives rise to the
following problems.
On-chip bus masters such as the direct memory access controller other than the CPU can access
internal memory other than the cache memory but cannot access the cache memory. If an on-chip
bus master other than the CPU writes data to an external memory other than the cache, the
contents of the external memory may differ from that of the cache memory. To prevent this
problem, if the external memory whose contents is cached is written by an on-chip bus master
other than the CPU, the corresponding cache memory should be purged by software.
internal memory other than the cache memory but cannot access the cache memory. If an on-chip
bus master other than the CPU writes data to an external memory other than the cache, the
contents of the external memory may differ from that of the cache memory. To prevent this
problem, if the external memory whose contents is cached is written by an on-chip bus master
other than the CPU, the corresponding cache memory should be purged by software.
In a cache-enabled space, if the CPU initiates read access, the cache is searched. If the cache stores
data, the CPU latches the data and completes the read access. If the cache does not store data, the
data, the CPU latches the data and completes the read access. If the cache does not store data, the