Renesas R5S72621 User Manual
Section 1 Overview
R01UH0134EJ0400 Rev. 4.00
Page 1 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Section 1 Overview
1.1
SH7262/7264 Features
This LSI is a single-chip RISC (reduced instruction set computer) microcontroller that includes a
Renesas-original RISC CPU as its core, and the peripheral functions required to configure a
system.
Renesas-original RISC CPU as its core, and the peripheral functions required to configure a
system.
The CPU in this LSI is an SH-2A CPU, which provides upward compatibility for SH-1, SH-2, and
SH-2E CPUs at object code level. It has a RISC-type instruction set, superscalar architecture, and
Harvard architecture, for superior rates of instruction execution. In addition, an independent 32-bit
internal-bus architecture enhances data processing power. This CPU brings the user the ability to
set up high-performance systems with strong functionality at less expense than was achievable
with previous microcontrollers, and is even able to handle realtime control applications requiring
high-speed characteristics.
SH-2E CPUs at object code level. It has a RISC-type instruction set, superscalar architecture, and
Harvard architecture, for superior rates of instruction execution. In addition, an independent 32-bit
internal-bus architecture enhances data processing power. This CPU brings the user the ability to
set up high-performance systems with strong functionality at less expense than was achievable
with previous microcontrollers, and is even able to handle realtime control applications requiring
high-speed characteristics.
This LSI has a floating-point unit and cache. In addition, this LSI includes on-chip peripheral
functions necessary for system configuration, such as a 64-Kbyte RAM for high-speed operation,
a 1-Mbyte or 640-Kbyte large-capacity RAM (32-Kbytes for 1-Mbyte and 320-Kbytes for 640-
Kbyte versions are shared by the data-retention RAM), multi-function timer pulse unit 2, compare
match timer, realtime clock, serial communication interface with FIFO, I
functions necessary for system configuration, such as a 64-Kbyte RAM for high-speed operation,
a 1-Mbyte or 640-Kbyte large-capacity RAM (32-Kbytes for 1-Mbyte and 320-Kbytes for 640-
Kbyte versions are shared by the data-retention RAM), multi-function timer pulse unit 2, compare
match timer, realtime clock, serial communication interface with FIFO, I
2
C bus interface 3, serial
sound interface, serial I/O with FIFO, controller area network interface*
2
, IEBus
TM
*
1
controller*
2
,
Renesas SPDIF interface, CD-ROM decoder , A/D converter, NAND flash memory controller,
USB 2.0 host/function, video display controller 3, sampling rate converter, SD host interface,
decompression unit, motor control PWM timer, and interrupt controller modules, and general I/O
ports.
USB 2.0 host/function, video display controller 3, sampling rate converter, SD host interface,
decompression unit, motor control PWM timer, and interrupt controller modules, and general I/O
ports.
This LSI also provides an external memory access support function to enable direct connection to
various memory devices or peripheral LSIs. These on-chip functions significantly reduce costs of
designing and manufacturing application systems.
various memory devices or peripheral LSIs. These on-chip functions significantly reduce costs of
designing and manufacturing application systems.
The features of this LSI are listed in table 1.1.
Notes: 1. IEBus (Inter Equipment Bus) is a trademark of Renesas Electronics Corporation.
2. This module is included or not depending on the product code.