Renesas R5S72621 User Manual

 

 

Section 10   Direct Memory Access Controller 
 

Page 400 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

1 NMIF 0 

R/(W)*

1

NMI Flag 

Indicates that an NMI interrupt occurred. When this bit 
is set, even if the DE bit in CHCR and the DME bit in 
DMAOR are set to 1, DMA transfer is not enabled. This 
bit can only be cleared by writing 0 after reading 1.*

2

 

When the NMI is input, the DMA transfer in progress 
can be done in one transfer unit. Even if the NMI 
interrupt is input while this module is not in operation, 
the NMIF bit is set to 1. 

0: No NMI interrupt 

1: NMI interrupt occurred 

[Clearing condition] 

Writing 0 after reading NMIF = 1*

2

 

0 

DME 

0 

R/W 

DMA Master Enable 

Enables or disables DMA transfer on all channels. If 
the DME bit and DE bit in CHCR are set to 1, DMA 
transfer is enabled. 

However, transfer is enabled only when the TE bit in 
CHCR of the transfer corresponding channel, the NMIF 
bit in DMAOR, and the AE bit are all cleared to 0. 
Clearing the DME bit to 0 can terminate the DMA 
transfer on all channels. 

0: DMA transfer is disabled on all channels 

1: DMA transfer is enabled on all channels 

Notes: 1.  Only 0 can be written to clear the flag after 1 is read. 

 

2.  If the flag is read at the same timing it is set to 1, the read data will be 0, but the internal 

state may be the same as reading 1. Therefore, if 0 is written to the flag, the flag will be 
cleared to 0 because the internal state is the same as when writing 0 after reading 1. 
For details, refer to section 10.5.2, Notes on Using Flag Bits.