Renesas R5S72621 User Manual
Section 10 Direct Memory Access Controller
Page 426 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Direct memory access controller
CH0 and CH1
Cycle steal mode
CPU
CPU
Priority: CH0 > CH1
CH0: Cycle steal mode
CH1: Burst mode
CH0: Cycle steal mode
CH1: Burst mode
Direct memory
access controller
CH1 Burst mode
Direct memory
access controller
CH1 Burst mode
CH0
CH1
CH0
CPU
DMA CH1
DMA CH1
DMA CH0
DMA CH1
DMA CH0
DMA CH1
DMA CH1
CPU
Figure 10.10 Bus State when Multiple Channels are Operating
10.4.5
Number of Bus Cycles and DREQ Pin Sampling Timing
(1) Number of Bus Cycles
When this module is the bus master, the number of bus cycles is controlled by the bus state
controller in the same way as when the CPU is the bus master. For details, see section 9, Bus State
Controller.
controller in the same way as when the CPU is the bus master. For details, see section 9, Bus State
Controller.
(2) DREQ Pin Sampling Timing
Figures 10.11 to 10.14 show the DREQ input sampling timings in each bus mode.
CKIO
DREQ
DACK
Bus cycle
(Rising)
(Active-high)
1st acceptance
2nd acceptance
CPU
CPU
CPU
Acceptance start
DMA
Non sensitive period
Figure 10.11 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection