Renesas R5S72621 User Manual
Section 11 Multi-Function Timer Pulse Unit 2
Page 448 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
11.3.3
Timer I/O Control Register (TIOR)
The TIOR registers are 8-bit readable/writable registers that control the TGR registers. This
module has a total of eight TIOR registers, two each for channels 0, 3, and 4, one each for
channels 1 and 2.
module has a total of eight TIOR registers, two each for channels 0, 3, and 4, one each for
channels 1 and 2.
TIOR should be set while TMDR is set in normal operation, PWM mode, or phase counting mode.
The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is
cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is
cleared to 0 is specified.
cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is
cleared to 0 is specified.
When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register
operates as a buffer register.
operates as a buffer register.
TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIORH_4
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IOB[3:0]
IOA[3:0]
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
7 to 4
IOB[3:0]
0000
R/W
I/O Control B0 to B3
Specify the function of TGRB.
See the following tables.
TIORH_0: Table 11.11
TIOR_1: Table
TIOR_1: Table
11.13
TIOR_2: Table
11.14
TIORH_3: Table 11.15
TIORH_4: Table 11.17
TIORH_4: Table 11.17
3 to 0
IOA[3:0]
0000
R/W
I/O Control A0 to A3
Specify the function of TGRA.
See the following tables.
TIORH_0: Table 11.19
TIOR_1: Table
TIOR_1: Table
11.21
TIOR_2: Table
11.22
TIORH_3: Table 11.23
TIORH_4: Table 11.25
TIORH_4: Table 11.25