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Renesas R5S72621 User Manual

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Section 11   Multi-Function Timer Pulse Unit 2 
 
R01UH0134EJ0400  Rev. 4.00  
 
Page 481 of 2108 
Sep 24, 2014 
 
 
 
SH7262 Group, SH7264 Group 
11.3.11
  Timer Counter (TCNT) 
The TCNT counters are 16-bit readable/writable counters. This module has five TCNT counters, 
one each for channels 0 to 4. 
The TCNT counters must not be accessed in eight bits; they should always be accessed in 16 bits. 
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note:
The TCNT counters must not be accessed in eight bits; they should always be accessed in 16 bits.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
11.3.12
  Timer General Register (TGR) 
The TGR registers are 16-bit readable/writable registers. This module has eighteen TGR registers, 
six for channel 0, two each for channels 1 and 2, four each for channels 3 and 4. 
TGRA, TGRB, TGRC, and TGRD function as either output compare or input capture registers. 
TGRC and TGRD for channels 0, 3, and 4 can also be designated for operation as buffer registers. 
TGR buffer register combinations are TGRA and TGRC, and TGRB and TGRD.  
TGRE_0 and TGRF_0 function as compare registers. When the TCNT_0 count matches the 
TGRE_0 value, an A/D converter start request can be issued. TGRF can also be designated for 
operation as a buffer register. TGR buffer register combination is TGRE and TGRF. 
Bit:
Initial value:
R/W:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note:
The TGR registers must not be accessed in eight bits; they should always be accessed in 16 bits. 
TGR registers are initialized to H'FFFF.